There is an increasing need for a high-density, high-speed, and low-power consumption SDRAM (Synchronous Dynamic Random Access Memory), which is one of popular semiconductor memories, with its generation evolving from SDR (single-data-rate) to DDR (double-data-rate). The generation of DDR is also evolving from DDR-1 to DDR-2. Furthermore, DDR-3 is expected to be put on the market as the next-generation DDR. Those DRAM generations differ primarily in the voltage of the supplied power. In particular, the power supply voltage of the data output unit is 2.5V for DDR-1 and 1.8V for DDR-2. The power supply voltage of the next-generation DDR-3 is expected to be 1.5V or lower.
On the other hand, there is a concept of developing a shared chip in which the internal circuits of SDRAM are shared across the generations of SDRAM with only the input/output circuit changed according to the generation. For example, Non-Patent Document 1 discloses a SDR/DDR compatible SDRAM. Sharing the circuits and educing the new design work in the shared parts lowers the development costs of a chip.
Patent Document 1 also discloses an output circuit that works at different power supply voltages and prevents the operation speed from being decreased, the power consumption from being increased, and a failure from occurring.
Non-Patent Document 2 discloses an example of the output circuit of a DDR-2 SDRAM. To output a high-speed output signal, a DDR-2 SDRAM is required to keep the waveform, the output impedance, and the amount of current of the output signal within those defined by the specifications. To meet these requirements, it is configured so that the signal for adjusting the output signal is output in synchronization with the output signal. For example, the output of the OCD (Off-chip driver) adjustment circuit that adjusts the amount of current of the output signal and the output of the ODT (On-die termination) adjustment circuit that terminates the output terminal (DQ bus) using a non-access chip are sent to the output terminal in synchronization with the major output of the output circuit.
[Non-Patent Document 1]
T. Sakata, et al., “A DDR/SDR-Compatible SDRAM Design with a Three-Size Flexible Column Redundancy,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 2000, p. 116–119.
[Non-Patent Document 2]
C. Yoo, et al., “A 1.8V 700 Mb DDR-II SDRAM with On-die Termination and Off-Chip Driver Calibration”, 2003 IEEE International Solid State Circuits Conference, IEEE, 2003, p. 312, p. 313, p. 495.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-8-65131 (FIG. 1).
The entire disclosures of the above prior art documents are incorporated herein by reference thereto.
Although an SDRAM allowing SDR and DDR to share the circuits for operation is conventionally disclosed, an SDRAM allowing DDR-1 an DDR-2 to share the circuits for operation is not know. To satisfy this need, one possible solution is to configure an SDRAM in which DDR-1 and DDR-2 share the internal circuits and each of DDR-1 and DDR-2 has its own output circuit. This configuration results in an increase in the output circuit size. Therefore, a high-density semiconductor chip with a reduced output circuit size cannot be fabricated by a combination of conventional technologies.